Nonvolatile memories typified by flash memories are used in a memory card for a digital camera etc., storage of BIOS for a personal computer, and so on as low power consumption memories capable of continuing to hold storage even after power has been turned off.
A stored value in a memory cell of the flash memory is determined by the amount of electrons accumulated in a floating gate as in cases where, for example, the value is 0 when the predetermined amount or more of electrons are accumulated in the floating gate and the value is 1 when electrons less than the predetermined amount are accumulated in the floating gate.
In the case where each of the values in the memory cells are determined in a manner as described above, changing a stored value in the memory cell to 0 is referred to as “writing”, and changing the stored value to 1 is referred to as “erasing” in general. “Writing” is performed by making a gate voltage sufficiently higher than a source voltage and a drain voltage. Through this operation, electrons are injected from a source region into the floating gate. On the other hand, “erasing” is performed by making the source voltage sufficiently higher than the gate voltage. Through this operation, electrons accumulated in the floating gate are pulled off into the source region. Since the erase operation causes damage to an insulating film under the floating gate, the lifetime of flash memories is determined by the number of times the erasing is performed.
Stored values in the flash memory cannot be rewritten with source electrodes or drain electrodes being grounded. Thus, by controlling all the voltages (source, drain, and gate voltages), the stored values can be rewritten. However, to control the three voltages for each of the memory cells, complexity in circuitry and size of a device increase. Hence, in general, the gate voltage is controlled by the sector including a plurality of the memory cells.
In cases where gate voltage is controlled by the sector, “writing” is performed by the memory cell, whereas “erasing” is performed by the sector. More specifically, when a stored value in a certain memory cell is rewritten from 0 to 1, data stored in all the memory cells of a sector including the memory cell is initially erased, and then verify processing is performed in order to check that stored values in the memory cells are 1, subsequently the value 0 is written into the memory cells where there has been no need to change the stored values to 1. At the result, only the stored values in the desired memory cells are finally rewritten from 0 to 1.
Since stored values in memory cells where there is no need to rewrite the stored values are also erased by performing the erase operation by the sector, the number of times the stored values in the memory cells are erased increases and therefore, the performance of the memory body, as well as that of the memory cells, degrades.
Therefore, as disclosed in Patent Reference 1, a semiconductor memory device has been proposed in which variations in the number of times erasing is performed by the sector are eliminated by providing reserve sectors aside from main sectors to store data in the memory cells of the sectors where the number of times erasing is performed is few. Since the occurrence of faulty sectors is suppressed by eliminating the variations in the number of times erasing is performed by the sector, the memory body can be used for a longer time.
[Patent Reference 1] Japanese Laid-Open Patent Publication No. 2002-366420 (pages 1-21 and FIG. 1)